CVE-2023-34326
x86/AMD: missing IOMMU TLB flushing
- State
- Published
- Severity
- 7.8 High
- Published
- Jan 5, 2024
- Updated
- Nov 4, 2025
- Reserved
- Jun 1, 2023
Description
The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed.
Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
Scores
| CVSS | Score | Vector | Source |
|---|---|---|---|
| 3.1 | 7.8 High | CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H | CISA-ADP |
Weaknesses
- CWE-672 Operation on a Resource after Expiration or Release
Affected Products
| Product | Versions |
|---|---|
XenXen |
|
References
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