CVE-2025-45006

State: Published
Severity: 9.1 Critical
Published: Jul 1, 2025
Updated: Jul 2, 2025
Reserved: Apr 22, 2025

Description

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

Scores

CVSS	Score	Vector	Source
3.1	9.1 Critical	CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H	CISA-ADP

Weaknesses

CWE-266 Incorrect Privilege Assignment

Affected Products

Product	Versions
n/an/a	n/aAffected

References

https://github.com/chipsalliance/rocket-chip.git
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications
https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md

Every record here comes from the CVE Program’s CVE List. © 1999–2026 The MITRE Corporation. CVE is a registered trademark of The MITRE Corporation. The records are reproduced under the CVE Program terms of use.