CVE-2025-63384
- State
- Published
- Severity
- 6.5 Medium
- Published
- Nov 10, 2025
- Updated
- Nov 12, 2025
- Reserved
- Oct 27, 2025
Description
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Scores
| CVSS | Score | Vector | Source |
|---|---|---|---|
| 3.1 | 6.5 Medium | CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N | CISA-ADP |
Weaknesses
- CWE-266 Incorrect Privilege Assignment
Affected Products
| Product | Versions |
|---|---|
n/an/a |
|
References
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