CVE-2025-8774
riscv-boom SonicBOOM L1 Data Cache timing discrepancy
- State
- Published
- Severity
- 2.0 Low
- Published
- Aug 9, 2025
- Updated
- Aug 12, 2025
- Reserved
- Aug 8, 2025
Description
A vulnerability has been found in riscv-boom SonicBOOM up to 2.2.3 and classified as problematic. Affected by this vulnerability is an unknown functionality of the component L1 Data Cache Handler. The manipulation leads to observable timing discrepancy. Local access is required to approach this attack. The complexity of an attack is rather high. The exploitation appears to be difficult. The vendor was contacted early about this disclosure but did not respond in any way.
Scores
| CVSS | Score | Vector | Source |
|---|---|---|---|
| 4.0 | 2.0 Low | CVSS:4.0/AV:L/AC:H/AT:N/PR:L/UI:N/VC:L/VI:N/VA:N/SC:N/SI:N/SA:N/E:P | VulDB |
| 3.1 | 2.5 Low | CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:L/I:N/A:N/E:P/RL:X/RC:R | VulDB |
| 3.0 | 2.5 Low | CVSS:3.0/AV:L/AC:H/PR:L/UI:N/S:U/C:L/I:N/A:N/E:P/RL:X/RC:R | VulDB |
| 2.0 | 1.0 Low | AV:L/AC:H/Au:S/C:P/I:N/A:N/E:POC/RL:ND/RC:UR | VulDB |
Weaknesses
Affected Products
| Product | Versions |
|---|---|
SonicBOOMriscv-boom |
|
References
- VDB-319297 | riscv-boom SonicBOOM L1 Data Cache timing discrepancyvdb-entry
- VDB-319297 | CTI Indicators (IOB, IOC, TTP)signaturepermissions-required
- Submit #625550 | SonicBOOM riscv-boom V2.2.3-210-gd77c2c3f implemented in Chipyard (V1.3.0) Improper Protection of Physical Side Channelsthird-party-advisory
- https://github.com/fizz-is-on-the-way/vuls_cpu/tree/master/MSHRushrelated
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