Riskcovery

CVE-2026-43191

drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35

State
Published
Severity
Not scored
Published
May 6, 2026
Updated
Oct 21, 2026
Reserved
May 1, 2026

Read the record on cve.org

Description

In the Linux kernel, the following vulnerability has been resolved:

drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35

[Why] A backport of the change made for DCN401 that addresses an issue where we turn off the PHY PLL when disabling TMDS output, which causes the OTG to remain stuck.

The OTG being stuck can lead to a hang in the DCHVM's ability to ACK invalidations when it thinks the HUBP is still on but it's not receiving global sync.

The transition to PLL_ON needs to be atomic as there's no guarantee that the thread isn't pre-empted or is able to complete before the IOMMU watchdog times out.

[How] Backport the implementation from dcn401 back to dcn35.

There's a functional difference in when the eDP output is disabled in dcn401 code so we don't want to utilize it directly.

Scores

The record has no CVSS score.

Weaknesses

The record names no weakness.

Affected Products

ProductVersions
LinuxLinux
  • ec129fa356bea5411cb16833cc5dab32689ea389 to before be43c36ac13d3a158791566c9fe60511022b7a15Affected
  • ec129fa356bea5411cb16833cc5dab32689ea389 to before 02b033e18e08a1d0b53cf540196688c82af60a2fAffected
  • ec129fa356bea5411cb16833cc5dab32689ea389 to before d1f7ceb00e8956ff6d183b7b45ef4e73c96f4c51Affected
  • ec129fa356bea5411cb16833cc5dab32689ea389 to before 75372d75a4e23783583998ed99d5009d555850daAffected
LinuxLinux
  • 6.7Affected
  • before 6.7Not affected
  • 6.12.114 through 6.12.*Not affected
  • 6.18.57 through 6.18.*Not affected
  • 6.19.6 through 6.19.*Not affected
  • 7.0 and laterNot affected

References

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